The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a level shifter 10 is shown. The level shifter 10 receives an input voltage Vin and generates an output voltage Vout. The level shifter 10 may include first and second NMOS transistors 12 and 14. A gate 16 of the first NMOS transistor 12 receives the input voltage Vin. An inverter 18 is connected between the gate 16 and a gate 20 of the second NMOS transistor 14. The level shifter 10 includes first and second PMOS transistors 22 and 24 connected in a flip-flop or half latch arrangement. In another configuration, the PMOS transistors 22 and 24 may receive the input voltage Vin and the NMOS transistors 12 and 14 may be connected in the flip-flop or half latch arrangement. In other words, the arrangement of the PMOS transistors 22 and 24 and the NMOS transistors 12 and 14 may be reversed.
Referring now to FIG. 2, a level shifter 30 may include first and second protection NMOS transistors 32 and 34 and first and second protection PMOS transistors 36 and 38. The first and second protection NMOS transistors 32 and 34 communicate with a first protection voltage Vprot1. Conversely, the first and second protection PMOS transistors 36 and 38 communicate with a second protection voltage Vprot2. The protection voltages Vprot1 and Vprot2 bias the protection NMOS transistors 32 and 34 and the protection PMOS transistors 36 and 38, respectively, to protect the level shifter 30 from excessive electric stress.
Referring now to FIGS. 1 and 2, the level shifters 10 and 30 communicate with input supply voltages Vss_in and Vdd_in and output supply voltages Vss_out and Vdd_out. Typically, the input supply voltage Vss_in is equivalent to the output supply voltage Vss_out, and the input supply voltage Vdd_in is not equivalent to the output supply voltage Vdd_out, although those skilled in the art can appreciate that the reverse is true when the positions of the NMOS transistors 12 and 14 and the PMOS transistors 22 and 24 are reversed.
The above described relationships between Vss_in and Vss_out and between Vdd_in and Vss_out may limit the operation of the level shifters 10 and 30. For example, in an NMOS driven level shifter, when Vss_out is greater than Vdd_in minus an NMOS threshold voltage Vt, the transistors 12 and 14 remain off regardless of whether a logical 0 or a logical 1 is applied to an input node. Consequently, the level shifters 10 and 30 will not function properly. Similarly, in a PMOS driven level shifter, when Vdd_out is less than Vss_in minus a negative PMOS threshold voltage Vt, the transistors 12 and 14 remain off. As a result, when an NMOS driven level shifter is used, an output low level needs to be equivalent to a logic low level (e.g. 0V, or a logical 0). Similarly, when a PMOS driven level shifter is used, an output high level needs to be equivalent to a logic high level (e.g. 3.3V, or a logical 1).